1. Field
Exemplary embodiments of the present invention relate to a cell array structure of a memory device, and more particularly, to a technology of substantially preventing data of a cell from being damaged due to coupling and the like between word lines of a memory device.
2. Description of the Related Art
[Background Art Related to Repair Operation of Memory Device]
FIG. 1 is a diagram for explaining a row repair operation in a conventional memory device.
Referring to FIG. 1, the memory device includes a cell array 110 including a plurality of memory cells, a row circuit 120 for activating word lines, and a row repair circuit 130 for a row repair operation.
The row repair circuit 130 stores row addresses, which designate normal word lines corresponding to failed memory cells in the cell array 110, as repair row addresses. For example, among 512 normal word lines NWL0 to NWL511, the row repair circuit 130 may store a row address corresponding to the third word line NWL3 and a row address corresponding to the 230th word line NWL230, as the repair row addresses. Furthermore, the row repair circuit 130 compares a row address R_ADD input from an exterior of the memory device with the stored repair row addresses. When the input row address R_ADD coincides with one of the stored repair row addresses, the row repair circuit 130 notifies the row circuit 120 of information indicating that the input row address R_ADD coincides with the stored repair row address.
The row circuit 120 activates a normal word line corresponding to the input row address R_ADD among the normal word lines NWL0 to NWL511 in an active operation. For example, when the row address R_ADD designates the fifth normal word line NWL5, the row circuit 120 activates the fifth normal word line NWL5. When the row circuit 120 is notified of information indicating that the input row address coincides with the repair row address from the row repair circuit 130, the row circuit 120 activates repair word lines RWL0 to RWL7 instead of the normal word lines NWL0 to NWL511. For example, when the input row address corresponds to the third word lines NWL3, the row repair circuit 130 notifies the row circuit 120 of information indicating that the input row address R_ADD coincides with the repair row address stored in the row repair circuit 130, and the row circuit 120 activates the 0th repair word line RWL0 instead of the third word line NWL3.
Through such an operation, among the normal word fines NWL0 to NWL511, failed normal word lines are replaced with the repair word lines RWL0 to RWL7. The number of the repair word lines may be changed according to design, and as the number of the repair word lines is increased, it is possible to repair many normal word lines.
[Background Art Related to Word Line Disturbance in Memory Device]
Meanwhile, as the degree of integration of the memory is increased, a pitch of a word line is gradually reduced, resulting in an increase in a coupling effect between word lines. Therefore, when the number of times, by which an activated state and a deactivated state of a word line are toggled, is increased, data of a memory cell connected to an adjacent word line may be damaged due to the coupling effect between word lines.
For example, in the case of a DRAM used as a main memory of a computer, a specific word line is repeatedly accessed many times (for example, 300K times) when the computer is booted, which frequently occurs. In such a case, due to electromagnetic waves generated by toggling of the specific word line repeatedly accessed, electrons are transferred to a capacitor of a cell connected to an adjacent word line or discharged from the capacitor, so that data may be damaged. Such a phenomenon is called a row hammer phenomenon.